Hardware Design for FPGAs

Following is a list of skills related to FPGA based hardware that will be learnt during this training.

• RTL level Design of FPGA based solution
• Implementation of RTL designs in Verilog
• Verification of RTL designs in Verilog
• FPGA selection for a given Application
• Optimizing the design for target FPGAs
• Solving design and synthesis issues
• Using FPGA cores and built-in components

Day 1: RTL Logic Design and Coding

• Logic design process at RTL
• Logic Building blocks
• Examples: Counter and FIFO
• Coding of synthesizable RTL blocks in Verilog

Day 2: Logic Verification

• Writing verification code in Verilog
• Example: FIFO Verification
• Methodical Verification
• Random, Directed and Mixed Verification techniques
• Example: FIFO Random verification

Day 3: State Machines and Synthesis

• State Machines and examples
• RTL Synthesis and Implementation: Pin assignment and clock constraints
• Synthesis and Implement reports

Day 4: Using FPGA Resources and Cores

• Explicit declaration of Xilinx components and simulation models
• Block RAM and Multipliers
• Using FPGA cores
• FIR Filter/DCM
• Timing: Identifying Critical paths
• Resource analysis, utilizing fixed resources
• Pipelining, re-timing, routing margins for timing

Day 5: Top Level Design

• Interfaces: Control and Data interfaces (ADC, DDC, PCI, LAN and USB ICs etc)
• Example: Ping pong buffer
• Memory Maps: Register file, usage of registers for configuration and control
• Coding of synthesizable RTL blocks in Verilog
• Verilog Modeling of external components
• Debug Support: Adding debug support

Thanks for your interest in our technical Trainings. This particular training is being offered from time to time on first come first serve basis to a group of 15-20 participants. Training will be offered when a minimum of 15 participants will get registered. For organizations on-demand training option is also available.

In order to register please click on the appropriate option below.

• Regular Training (individuals)
• On-Demand Training

Who Should Attend ?

Engineers targeting FPGA or ASIC design as their career having

• Little or No practical experience on FPGAs
• Having some practical experience on limited problems

Pre-Requisites

• Basic knowhow of tools like Matlab/Octave.
• Fundamental concepts of digital signal processing and communications

Tools and Equipment

• ModelSim
• SE® Design Suite

Following is a list of skills related to FPGA based hardware that will be learnt during this training.

• RTL level Design of FPGA based solution
• Implementation of RTL designs in Verilog
• Verification of RTL designs in Verilog
• FPGA selection for a given Application
• Optimizing the design for target FPGAs
• Solving design and synthesis issues
• Using FPGA cores and built-in components

Day 1: RTL Logic Design and Coding

• Logic design process at RTL
• Logic Building blocks
• Examples: Counter and FIFO
• Coding of synthesizable RTL blocks in Verilog

Day 2: Logic Verification

• Writing verification code in Verilog
• Example: FIFO Verification
• Methodical Verification
• Random, Directed and Mixed Verification techniques
• Example: FIFO Random verification

Day 3: State Machines and Synthesis

• State Machines and examples
• RTL Synthesis and Implementation: Pin assignment and clock constraints
• Synthesis and Implement reports

Day 4: Using FPGA Resources and Cores

• Explicit declaration of Xilinx components and simulation models
• Block RAM and Multipliers
• Using FPGA cores
• FIR Filter/DCM
• Timing: Identifying Critical paths
• Resource analysis, utilizing fixed resources
• Pipelining, re-timing, routing margins for timing

Day 5: Top Level Design

• Interfaces: Control and Data interfaces (ADC, DDC, PCI, LAN and USB ICs etc)
• Example: Ping pong buffer
• Memory Maps: Register file, usage of registers for configuration and control
• Coding of synthesizable RTL blocks in Verilog
• Verilog Modeling of external components
• Debug Support: Adding debug support

Thanks for your interest in our technical Trainings. This particular training is being offered from time to time on first come first serve basis to a group of 15-20 participants. Training will be offered when a minimum of 15 participants will get registered. For organizations on-demand training option is also available.

In order to register please click on the appropriate option below.

• Regular Training (individuals)
• On-Demand Training