We are involved in the joint development of an L-band, ground to air, electronically steered phased array radar system (ESPAS). It is basically a 32 elements, pulse Doppler, moving target indication (MTI) radar with relatively low pulse repetition frequency (PRF). ESPAS is a funded project and being jointly developed by Renzym, Technology Nucleus and Bismillah Electronics. It is a pilot project for full fledged radar for ground surveillance.
ESPAS is software-defined modern radar prototype which offers flexibility and reprogram-ability inherent in the digital design. Key radar parameters like PRF, pulse duration, pulse compression, beam-forming algorithm, CFAR, pre-filter etc can be readily programmed to meet the desired performance specifications. This prototype not only serves as a proof of concept but will also be used to fine tune the specifications for its next phase which would be a scaled up full-fledged ground surveillance radar. The overall ESPAS development has been divided into three major areas.
- Radar Signal Processing Algorithms
- Embedded Implementation on FPGA based Hardware Platform
- Radar Analog Front End
Renzym is responsible for embedded development of FPGA based hardware platform which comprises Innovative Integration’s two Quadia cards, two TX XMC modules and two DR XMC modules. We have carried out the fixed point implementation within the specified performance criteria and real time embedded implementation of the radar signal processor (RSP).
Technology Nucleus is responsible for Radar algorithm development and coordination between all the involved parties. Bismillah Electronics is developing the ESPAS Analog front end hardware. The project is in the final phases of its completion. Field trials are expected to start by December 2010.
Company Name
20 Feb, 2018
Business Consulting
Specifications
ESPAS Subsystems
- Analog Front End (AFE)
- Radar Signal Processor (RSP)
- Display and Data Processor (DDP)
ANALOG FRONT END (AFE)
In the receiver (Rx) signal chain, AFE (not shown in the above Figure) constitutes a superheterodyne radar receiver. Its core function is to amplify, down convert (from RF to IF) and filter the incoming signal so as to prepare it for radar signal processing. Tx and Rx chains are developed for 8×4 rectangular antenna array i.e. there are 8 columns and 4 rows.
RADAR SIGNAL PROCESSOR (RSP)
Job of RSP is to improve the received target-to-clutter power ratio to a level where target detection can be made possible even if it is hiding in a strong clutter. In the Rx signal chain, RSP processes the signal captured from the AFE and presents its results to the host PC. In the Tx signal chain, it generates pulse train for each of the antenna elements. RSP is performed on the signal processing card in either signal chain. Eight active antenna elements require eight DACs in the Tx path and eight ADCs in the Rx path.
DISPLAY AND DATA PROCESSOR (DDP)
DDP takes information about the target from the RSP card via PCI interface and displays it to the operator. Moreover, it is also used as a graphical interface to configure various parameters of the Tx and Rx signal processing chains. DDP runs on an industrial-grade PC.
Hardware Platform
The target implementation platform of radar signal processor (RSP) is based on Innovative Integration’s Quadia card. Quadia is a processing baseboard card with PCI interface that can carry two XMC modules. Two Quadia cards are employed in the RSP; one for Tx chain and the other for Rx chain. Quadia card – when employed in the Tx chain – carries Innovative Integration’s two TX XMC modules. Each TX module contains Two 1 GSPS 16-bit, DAC and One XC2VP40 VirtexII-Pro FPGA. Quadia card – when employed in the Rx chain – carries Innovative Integration’s two DR XMC modules. Each DR module contains four LTC2255, 14-bit, 125 MSPS ADCs, four TI’s GC5016 chips as DDCs and one XC2VP40 VirtexII-Pro FPGA. At one end, these Quadia cards interface with analog front end (AFE) via ADCs or DACs while at the other end, they are interfaced with industrial grade PC via PCI interface as illustrated below.
