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Renzym Education

We intend to upload videos covering various courses as well as tutorials on applying theory in practice. Most of these videos are collaborative work of Abasyn University Islamabad Campus and RENZYM.

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This is Urdu version of a video that I already made in English (English version: ). In the video I tried to simplify understanding of complex numbers, imaginary numbers and Eular’s formula in a way typically not covered in standard texts. I had some unanswered questions about imaginary numbers since a couple of decades. During covid days I spent some time and answered those that led to the original video.While teaching my kids I realized that there should be an Urdu version too so I made this one (Matric maths text books don’t provide any visual understanding). Feel free to See MoreSee Less
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𝐅𝐢𝐫𝐬𝐭 𝐯𝐢𝐝𝐞𝐨 𝐭𝐨 𝐜𝐫𝐨𝐬𝐬 100𝐊 𝐯𝐢𝐞𝐰𝐬 𝐨𝐧 𝐦𝐲 𝐲𝐨𝐮𝐭𝐮𝐛𝐞 𝐜𝐡𝐚𝐧𝐧𝐞𝐥. Took about 2 years in doing so, organically.The back story is that when we started Renzym, HW training was planned to be one of our business directions. So I prepared these slides for that, but due to existing projects we only conducted the training a couple of times.I started using those slides in logic design course, and during COVID days I created different sections. I stiched those into a single video that can get people started in Verilog in a short span. Since then, I have been using it to train people during internships and training period at Renzym. And I hope the other 100K have somewhat benefitted from it too.It does not require any prerequisites as such. So anyone wanting to explore the field of HW design can peek and try out.This was also the first major content that I converted to English on my channel to spread it to a wider audience. I created a few more and have plans to convert more of existing content (e.g. Zynq training, that internees/trainees follow up next) into English if/when time allows (So do subscribe and press the bell icon 😉 ).Thanks for watching and feel free to share. See MoreSee Less
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This is a complete computer architecture course in Urud/Hindi which covers most of the content from freely available UC Berkeley’s computer architecture course slides.On Eid holidays, I decided to spend a few hours on a couple of my existing playlists to remove redundancies in videos and join them to have a single video. Well, few hours took up all the holidays, but in the end I was able to cut down a 22 hours playlist into a 12 hours video.One of the motivations was that there has been a lot of work lately in RISCV based processors, but engineers often have holes in their understanding. I could not find a resource that could do it minimum time, so I thought to create one. I intended to keep it to 5-6 hours, but there were so many topics that it ended up to 12 hours divided into six sections:1. Single Cycle Processor (~1 hr)2. Pipelining and Branch prediction ( ~2 hrs)3. Memory (Caches and VM) ( ~3 hrs)4. Complex Pipelines ( ~2 hrs)5. VLIW, Multithreading, Vector processors ( ~2 hrs)6. Synchronization and Cache Coherence ( ~2 hrs)Feel free to share.#computerarchitecture See MoreSee Less
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In this video we demystify the boundary between hardware and software at lower level. Its useful for everyone. No pre-requisites required as everything required is covered. Its useful as a first intro video to processor design. We designed a small processor from scratch, wrote its Verilog code (we covered what Verilog is) and simulated it. Verilog code link for this small processor is there in the video description.I already covered similar content earlier, but I tried to simplify and shorten it to make it easier as well as concise. Feel free to share it to whoever might be interested. See MoreSee Less
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