We intend to upload videos covering various courses as well as tutorials on applying theory in practice. Most of these videos are collaborative work of Abasyn University Islamabad Campus and RENZYM.
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Abasyn Islamabad: http://www.abasynisb.edu.pk
Facebook: https://www.facebook.com/renzymeducation
Abasyn Islamabad: http://www.abasynisb.edu.pk
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This week in the first lecture we concluded Caches & VM related section of the course. We discussed how we can reduce latency introduced by TLB by using virtually addressed caches. This led to aliasing problems and we discussed solutions for that. Finally we discussed that page table size could could be addressed by using PPN as index, but we had to use hashing to avoid comparing every location.![]()
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In 2nd lecture, we started new topic of complex pipelines including FP units. We discussed the first major approach i.e. Scoreboard to allow out-of-order completion of instructions.![]()
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Page fault handling, Virtual address caches, Hashed page tables, Computer Architecture Lec 19 / 30
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Course material: tinyurl.com/ca-renzymTopics Covered:(00:00) Review of translation and VM(13:36) Handling page faults(27:14) Coping with translation … This week (2 lectures) we covered address translation in detail. ![]()
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Started with base and bound scheme to support running multiple programs on our previously bare machine. Then we discussed fragmentation issue in this approach and resolved it using paged memory system. Paged memory system led to increased memory requirement due to page table size, which was resolved using hierarchical page tables. But this led to multiple memory accesses before accessing the real location we want to access slowing everything down. This was resolved using a Translation look aside buffer (TLB) to cache the translations. In the end we saw where everything fits in the classic 5-stage pipeline example.![]()
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There are a few more topics to touch in translation and virtual memory that we shall cover after Eid holidays. A happy Eid to everyone.![]()
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Address Translation, Base and bound, Paged memory system, Computer Architecture Lec 17 / 30
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Course material: tinyurl.com/ca-renzymTopics Covered:(00:00) Quiz anouncement(02:12) Victim cache`(05:00) Bare machine(09:46) Dynamic address transla… This week we concluded our discussion on caches in two lectures covering several topics like where does cache fit in the classis 5-stage pipeline, replacement policies, cache performance measurements, reducing read penalty using write buffer, multi-level caches, and some real-world examples.![]()
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We had a third lecture this week solely focused on problem solving for midterm prep. The best way to utilize that session is to pause the video after the question and try to solve yourself, and then watch the solution to compare your approach against instructor’s.![]()
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Replacement policy, Write policy, Cache performance, Computer Architecture Lec 14 / 30
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Course material: tinyurl.com/ca-renzymTopics Covered:(00:00) Review of placement policies`(07:30) Replacement policy: LRU, FIFO, NMRU(15:08) CPU-Cach… This week (two lectures) we discussed memories and caches. We discussed rationale behind caches. We discussed how power of two chunks make it easier to divide addresses (Be it rows and columns in case of DRAMs, or dividing cache addresses into Block no (Tag+Index) and block offsets). We covered Directly mapped, Set associative and Fully Associative caches.![]()
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Next week we shall focus on how caches fit in the 5-stage pipeline, various smaller topics about caches and if time allows, we shall move towards virtual memory.![]()
Memories and caches I, Computer Architecture Lec 12 / 30
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Course material: tinyurl.com/ca-renzymTopics Covered:(00:00) Review of Memory intro(02:34) How Dividing address into Rows & Cols work(14:45) Latency … This week’s 2 lectures covered Control hazards, Exceptions and interrupt handling in classic 5 stage pipeline. Then we reviewed a bit deeper pipeline example of MIPS R4000, and the we reviewed initial supercomputers like Crey-1 CDC6600. Finally we discussed issues in complex in-order issue pipelines. This concluded Pipelining related discussion in the course (which is the second major chunk after unpipelined processor design).![]()
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Next week we shall be focusing on third chunk i.e. Caches and Virtual Memory.![]()
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Control hazards, Exception/Interrupts handling, Branch delay slot, Computer Architecture 10 / 30
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Course material: tinyurl.com/ca-renzymTopics Covered:(00:00) Review of pipelining, interlock and bypass(07:11) Control Hazards: PC Calculation(12:21)… This week’s two lectures covered RISCV (RV32I) instructions format, Hardwired control logic and and Pipelining. ![]()
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Around 20 minutes (starting 19:40 in the first lecture) cover almost all instructions in RV32I except the ones required for OS/Debug/Atomic operations (which shall be cover later). Can be a reasonably good reference any time when wants to revise base instructions.![]()
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We then discussed how hardwired control logic can be designed for single cycle processor, followed by Classic 5-Stage RISC Pipeline, Iron Law, different kinds of hazards and strategies to resolve those like Interlocks/Stalls and Bypassing/Forwarding.![]()
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RISCV instructions (RV32I), Control Logic, Pipeline intro, Computer Architecture Lec 08 / 30
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#RISCV #RV32I #instructionformat Course material: tinyurl.com/ca-renzymImages taken from this book (also links to his own lectures on this page): htt…